1. Field of the Invention
The invention relates to design layout processing, and in particular to using pre-processed structures to accelerate optical proximity correction (OPC) of the design layout.
2. Description of the Related Art
Optical proximity correction (OPC) applies systematic changes to geometries of a layout to improve the printability of a wafer pattern. Specifically, as the size of integrated circuit features drops to 0.18xcexc and below, the features can become smaller than the wavelength of the light used to create such features, thereby creating optical distortions when printing the features onto the wafer. These optical distortions can represent significant impacts on device performance.
Rule-based OPC can include rules to implement certain changes to the layout, thereby compensating for some optical distortions. For example, to compensate for line-end shortening, rule-based OPC can add a hammerhead to a line end. Additionally, to compensate for corner rounding, rule-based OPC can add serif shapes to outer corners or subtract serif shapes from inner corners. These changes can form features on the wafer that are closer to the original intended layout.
In model-based OPC, a real pattern transfer can be simulated (i.e. predicted) with a set of mathematical formulas (i.e. models). In model-based OPC, the edges of a feature in a layout can be dissected into a plurality of segments, thereby allowing these segments to be individually moved to correct for proximity effects. The placement of the dissection points is determined by the feature shape, size, and/or position relative to other features, by simulation, or wafer results. Dissection points can also be determined by exploring the proximity behavior along the edges. In some embodiments, a fixed dissection length can be used for edges, e.g. every N nm. In other embodiments, multiple dissection lengths are provided, e.g. inner corner, outer corner, etc.
FIG. 1 illustrates a simplified flow chart for standard OPC processing. Specifically, in step 101, a chip layout can be received. In one embodiment, the data input format of the layout can include hierarchical information, i.e. information organized into a hierarchy of cells, each cell containing a portion of the layout data. In such an embodiment, hierarchical information can be xe2x80x9cflattenedxe2x80x9d into shapes associated with a single layer of the chip. Alternatively, the hierarchy can be modified to account for proximity effects between different cells. This flattening or modifying facilitates shape identification, which can be used when performing OPC in step 102. A modified chip layout can be output in step 103.
Step 102 can include rule-based OPC, model-based OPC, or a hybrid of rule- and model-based OPC. In general, model-based OPC provides higher accuracy, but can take significantly more time to process the layout than rule-based OPC. In one embodiment of hybrid OPC, rule-based OPC is performed on predetermined locations on the layout and model-based OPC is performed on other locations. In this manner, hybrid OPC can provide an intermediate level of accuracy and processing time.
Typically, performing OPC is done toward the end of the chip design process. Thus, OPC can become a bottleneck for implementing a chip layout. Growing design sizes and increasing complexity of OPC methodologies can aggravate this problem. Thus, performing OPC can result in undesirable long runtimes as well as large disk/memory requirements.
Therefore, a need arises for increasing OPC speed and decreasing disk/memory requirements associated with OPC. Note that the term OPC as used herein can generically refer to proximity effect corrections, e.g. for resist, etch, and micro-loading.
Performing optical proximity correction (OPC) is typically done during tape out of the mask data needed to manufacture the integrated circuit. Unfortunately, this period can be extremely critical, wherein even small delays in finishing OPC can have significant adverse effects on product introduction and/or market exposure. In accordance with one feature of the invention, repeating structures in library elements (e.g. standard cells) and/or layout data (e.g. portions of a chip layout, IP cores, memory cells, and/or input/output blocks) can be identified during a non-critical time. Repeating structures can be defined as xe2x80x9cstaticxe2x80x9d structures having identical or substantially similar proximity effect (e.g. optical) environments. Static structures can be any structures that will not change during the chip design process. Therefore, OPC can also be performed on representative repeating structures during a non-critical time. In typical layouts, this pre-processing can provide OPC solutions for at least half of a design. Thus, using pre-processing can dramatically minimize any OPC impact on downstream scheduling for the integrated circuit.
Structures can be identified at micro and macro levels. For example, structures can include segments, shapes (i.e. portions of polygons), polygons, and group of polygons. In one embodiment, structures within an inner core of a cell can be analyzed. For example, the core can be defined as an area within a cell that is inward by a distance equal to the proximity effect range from the cell proximity effect boundary (i.e. the area around the cell that is guaranteed not to contain any shapes on the same layer from adjacent cells). In one embodiment of the invention, identification of the repeating structures and the pre-processing of representative repeating structures can be done during the creation of the library elements/layout data. In this manner, the structures and/or positions of the structures in the library elements/layout data can be modified, if possible, to maximize the number of repeating structures. In general, identification of the repeating structures and the pre-processing of representative repeating structures can be done whenever the resources needed to perform OPC (e.g. CPU or microprocessor time) are available.
Information regarding the pre-processed structures can be stored until needed. This information can include dissection and evaluation points for segments, contrast images at the evaluation points, and a corrected version of the structure. In one embodiment, the pre-processed structure information can be stored with the library element or layout data, e.g. as part of a layer of the hierarchy or on a layer dedicated to pre-processed structure information. In another embodiment, the pre-processed structure information could be kept in a separate data file associated with the library or layout data. In one implementation, the library elements, the layout data, and/or the pre-processed repeating structure information can be provided in GDS-II format.
Advantageously, after pre-processing a representative repeating structure in a set of repeating structures, other structures in the set can be instantiated (i.e. the OPC solution for the representative repeating structure can be copied at designated locations), thereby eliminating the need to compute the OPC for those other structures. Thus, an OPC tool can use the pre-processed structures in conjunction with a chip layout to quickly generate a modified layout, thereby saving valuable computing time. For example, in one embodiment, the pre-processed representative structures can be computed before instantiating them into the design. Moreover, because a chip layout typically includes multiple repeating structures, pre-processing also decreases data volume. Specifically, the instantiations create more hierarchical data, which take up significantly less volume than flat layout data.